1. Field of the invention
The invention relates generally to a method for rounding trench corners of an integrated circuit device. More particularly, the invention relates to a method of forming an offset for an isolation trench by using disposable oxide spacers and subsequently rounding the trench corners by high temperature oxidation.
2. Related Art
Various methods have been developed to isolate devices within integrated circuits. One of the methods is known as trench etch and refill. In this method, a trench is etched into a substrate and is filled with a chemical vapor deposition (CVD) oxide. The etched trench may be shallow (depth&lt;1 .mu.m), of moderate depth (1.mu.m.ltoreq.depth.ltoreq.3.mu.m), or deep and narrow (depth&gt;3.mu.m and width&lt;2.mu.m). Deep and narrow trenches refilled with CVD oxide are particularly useful for preventing latchup and for isolating n-channel from p-channel devices in CMOS circuits.
Fabrication of trenches, however produces parasitic edge transistors at the corners of the trench sidewalls. Parasitic edge transistors are not desired because they increase the OFF current of the devices of the integrated circuit and increase the susceptibility to latchup. Parasitic edge transistors also turn on at a lower voltage than the active device, thereby causing a phenomenon known as a "subthreshold kink" in the current-voltage (I-V) characteristic curve.
FIG. 1 shows a conventional deep-and-narrow isolation trench structure. A silicon substrate 120 is formed with trenches 124. Trenches 124 are filled with an oxide 128 to isolate active devices from each other. A gate oxide 132 covers the substrate 120 and the oxide 128 in the trenches 124. A gate polysilicon (poly) electrode 136 is on top of the gate oxide 132 and positioned over the substrate 120 to form an active device with the ends of the gate poly electrode 136 extending over a portion of the trenches 124.
The oxide 128 is formed with dimples in the trenches 124. The dimples are caused by overetching of a sacrificial oxide (sacox) prior to forming the gate oxide 132. When the gate oxide 132 and the gate poly electrode 136 are added, they recess partially into the trenches 124.
The conventional structure, as shown in FIG. 1, forms parasitic edge transistors at the corners of the trenches 124. The recessed portion of the gate poly electrode 136 acts as a gate electrode of the parasitic transistor and the portion of the gate oxide between the recessed portion and the side wall of the trench 124 acts as a gate oxide of the parasitic transistor.
Further problems occur due to a thinning of the gate oxide 132 at the corners of the trenches 124 where the gate oxide 132 recesses into the trenches 124. Thinned gate oxide decreases reliability and increases the electric field strength at the trench corner, thereby exacerbating the above discussed problem regarding parasitic transistors.